IEEE International Electron Devices Meeting(IEDM)is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.

CIRCUIT AND DEVICE INTERACTION (CDI)

Papers are solicited in the areas of CMOS platform technology, circuit design challenges at advanced nodes, and device technology co-optimization solutions. Platform technologies include beyond Si channel such as SiGe/Ge, and advanced device technologies such as Gate-all-around Nanowire and Stacked Nanosheet CMOS technologies are of strong interest. Topics also include digital and analog device and circuit performance and scaling issues, power-performance-area analysis, and architectural implications of interconnect technology and performance. Submission of papers discussing interactions between advanced device technology and design issues such as variability, aging, power constraints, physical layout effects and design is encouraged. Papers addressing stacked and monolithic 3D integration, interconnect bottleneck and design challenges are solicited. Emerging circuit design and technology concepts supporting new computing models such as processing-in-memory, machine learning acceleration, neuromorphic computing, and other non-von Neumann computing approaches are of interest.

CHARACTERIZATION, RELIABILITY and YIELD (CRY)

Papers are solicited in all areas of electrical and physical characterization, reliability evaluation and yield analysis of transistors, interconnects and circuits. Specific reliability topics include, for FEOL: transistor degradation due to hot carriers and bias temperature instabilities; dielectric wear‐out and breakdown; self-heating effects; process charging damage; latch‐up and ESD; soft error mechanisms in logic and memories and error correction techniques; noise and mismatch behavior. For MEOL/BEOL topics include: electromigration failure of contacts and interconnects; breakdown of BEOL dielectrics and MEOL spacers; mechanical stress-related mechanisms;thermal management; chip‐package interaction. Of particular interest are investigations of degradation mechanisms for: resistive devices; emerging memories; III-V power devices, and More-than-Moore applications. Also solicited are papers discussing variability / reliability interactions and failure analysis techniques.

COMPOUND SEMICONDUCTOR AND HIGH SPEED DEVICES (CHS)

Papers are solicited in the areas of compound semiconductor electronic devices and high-speed device technologies based on GaAs, InGaAs, InP, GaN, InAlN, Si, SiGe, Antimonides and their related alloys. Devices of interest include III‐V MOSFETs, ballistic devices, HBTs (III-V and group IV) and HEMTs, RF/microwave/millimeter‐wave/THz devices, SAW/BAW devices, low noise amplifiers, RF power amplifiers, RF and millimeter-wave switches and filters, and active and passive electron devices for analog applications. Topics include device physics, design, modeling, reliability and manufacturing processes.

MEMORY TECHNOLOGY (MT)

Papers are solicited covering all memory technology topics, including storage-class and embedded memories, as well as in-memory and neuromorphic computing applications. Topics span from novel cell concepts to fully integrated memories, from prototyping to manufacturing issues and performance. Specific areas of interest include both conventional and novel memory cells including ReRAM, STT‐MRAM, PCRAM, FeRAM, 3D NAND, crosspoint and selectors, organic memory and NEMS‐based devices, including their design and scaling, processing, reliability, and modeling. Novel concepts and demonstrations that enhance memory properties or apply to neural computing paradigms are of interest. Higher level topics include 3D architectures, novel read/program/erase schemes, solid state drive (SSD) applications, novel hierarchies and architectures for memory-centric systems, security, computing-in-memory and non‐volatile memory-enabled emerging logic applications.

MODELING and SIMULATION (MS)

Papers are solicited in the areas of analytical, numerical, and statistical approaches to model electronic, optical, hybrid devices including sensors, and their isolation and interconnects. Topics include physical and compact models for logic and memory devices (e.g. steep-slope devices, RRAM, CBRAM) and interconnects, modeling and emulation of fabrication processes and equipment, material modeling, parameter extraction, compact models for advanced technologies and novel devices, performance evaluation, reliability, variability, and benchmarking methodologies. Other topics include novel computing approaches (e.g. neuromorphic computing) and modeling of interactions between process, device, circuit, and packaging. Submissions should advance the art of modeling and simulation or apply existing techniques to gain new device insights.